1. Field of the Invention
The present invention relates to an interface between a data link layer and a physical layer. In particular, the present invention relates to a serial interface that conforms to SMII (Serial Media Independent Interface).
2. Description of Related Art
In a computer system utilizing the Ethernet (registered trademark), an interface that conforms to such as MII (Media Independent Interface) defined by IEEE 802.3, RMII (Reduced Media Independent Interface) or SMII defined by a vendor is widely used as an interface between MAC (Media Access Control) and PHY (Physical layer device).
The SMII as the MAC/PHY interface specification is used preferably in a processor, an FPGA, an Ethernet (registered trademark) transceiver and the like. In the vendor-defined SMII, signal lines in the MII are serialized in order to reduce the number of signals related to transmission/reception of data and control information. Techniques related to the SMII are described, for example, in U.S. Pat. No. 6,385,208, U.S. Pat. No. 7,227,869, Non-Patent Document 1 (“Serial-MII Specification”, Revision 2.1 ENG-46080, Feb. 9, 2000, CISCO SYSTEMS <http://www.angelfire.com/electronic2/sharads/protocols/MII_Protocols/smii.pdf>), Non-Patent Document 2 (“PE-SMII Serial MII I/F for Inventra's Ethernet MACs datasheet”, Mentor <http://www.mentor.com/products/ip/ethernet/10—100_mbps/upload/pe_smii_pd.pdf>), and Non-Patent Document 3 (“KSZ8041TL/FTL Data sheet Rev.1.1, April 2007, pp 24-26, Micrel <http://download.siliconexpert.com/pdfs/2008/03/06/se mi_ap/manual/mcl/ds/ksz8041t1-ftl.pdf>).
Among the MII specification, the SMII is the smallest in the number of pins per a port. For example, the number of pins per a port is six (two for data and four for control signals). Moreover, in the case of the SMII, two operation speed modes of 10 Mbps and 100 Mbps are prepared and can be switched. It should be noted that in either mode (10 Mbps, 100 Mbps), the same reference clock of 125 MHz is used for data transfer.
FIG. 1 is a timing chart showing a data transmission operation (10 Mbps) between the MAC and the PHY that conforms to the SMII according to the related technique. Here, as an example, let us explain an operation of transferring data from the MAC to the PHY at a transmission rate of 10 Mbps. A clock signal TX_CLK is generated in synchronization with a reference clock generated on a system board, and is input to the PHY and the MAC. It should be noted that the reference clock may be generated by the MAC. The clock signal TX_CLK is a successive 125 MHz clock and serves as a basis for transmission timing of a transmission data TX.
A synchronization signal TX_SYNC is generated by the MAC based on the reference clock and is input to the PHY. The synchronization signal TX_SYNC indicates a boundary between segments in a transmission data or a reception data. Each segment has a 10-bit width. That is, the synchronization signal TX_SYNC is generated every ten cycles of the clock signal TX_CLK.
The transmission data TX output from the MAC to the PHY within one segment includes byte data TXD0 to TXD7 and transmission control information (error information TX_ER and enable information TX_EN). The data transmitted within one segment is hereinafter referred to as a segment data DATA. In the case of the 10 Mbps mode, an update cycle of the segment data DATA is once per ten segments. Therefore, the MAC outputs an identical segment data DATA to the PHY in synchronization with the synchronization signal TX_SYNC, until the segment data DATA (byte data) is updated. That is, the identical segment data DATA is output repeatedly for ten times from the MAC to the PHY. In the case of the 10 Mbps mode, the PHY can extract the segment data DATA just by sampling any one of the ten segments.
On the other hand, in the case of the 100 Mbps, the segment data DATA is updated for each segment. That is, the segment data DATA is updated in synchronization with the synchronization signal TX_SYNC, and the data sampling in the PHY is performed at a timing in synchronization with the synchronization signal TX_SYNC.
The inventor of the present application has recognized the following points. As described above, the segment data is updated every segment in the case of the 100 Mbps mode, while the segment data is updated once per ten segments in the case of the 10 Mbps mode. Therefore, in the case of the 10 Mbps mode, one segment data among the identical ten segment data just needs to be sampled. However, the segment data other than the sampled one are wasted. In FIG. 1, for example, only the segment data #S1 among ten segment data #S1 to #S10 is sampled in the PHY, and the other segment data #S2 to #S10 become ineffective data. In this case, a period used for transferring the ineffective segment data #S2 to #S10 is nine-times longer than a period required for transferring the effective segment data #S1. During the ineffective period, power is unnecessarily consumed in both of the MAC and the PHY for driving circuits and buffers.
This results from the specification that the PHY as the receiving side just needs to sample either one of the ten segments (refer to the above-mentioned Non-Patent Document 1). To put it the other way around, since the sampling timing in the PHY can be set arbitrarily, the MAC needs to output the identical segment data until the next data update timing.
Moreover, according to the related technique, the frequency of the clock signal TX_CLK is the same 125 MHz in both the 10 Mbps mode and the 100 Mbps mode. In general, power consumption increases in proportion to the driving frequency. In the case of the interface that conforms to the SMII, the driving frequency does not vary even when the transmission rate is changed. Therefore, in the case of the 10 Mbps mode, the clock frequency is relatively high and thus the power consumption for outputting the above-mentioned ineffective data further increases.